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What we offer

We design, verify and prototype digital chips and FPGA systems. Here is what you can work with us on today.

Talk to an engineer

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Chip and FPGA design services

Digital design, verification and FPGA prototyping for engineering teams that need extra capacity. We work from the physics of your problem to tested digital logic, and we document every step so your team can own the result.

Packages and prices

Fixed price per milestone. Packages from US$1,200.

  1. A1

    Interface and peripheral block

    UART, SPI, I²C, PWM, timers, GPIO and checksum engines, with a self checking testbench and a verification report.

  2. A2

    Sensor chip logic

    Digital logic for sensor chips: reading sensors, filtering, event detection and packet output. The same class of design as Raven-01.

  3. A3

    Verification of your RTL

    A test plan, testbench, independent reference model, regression suite and coverage report for a block you designed.

  4. A4

    RTL audit and lint report

    A review of your code for bugs, unsafe constructs, clock domain issues and style, with a prioritised list of fixes.

  5. A5

    FPGA proof sprint

    A verified design taken onto your FPGA board in two to three weeks, with timing closure, bring up and a recorded demonstration.

GUARANTEE

Pay for results. Every milestone has written acceptance tests. If a delivered milestone still fails them after two rounds of fixes, you get that milestone's fee back.

Founding clients: our first three clients receive 25% off any package.

FPGA proof sprint

A fixed price sprint of two to three weeks. You bring one function you need in hardware. We design it, verify it against an independent reference model, and implement it for your FPGA.

LENGTH
Two to three weeks
PRICE
Fixed, agreed in writing before we start
YOU GET
The design, its tests, the reference model and a written report
GUARANTEE
Pay for results. Every milestone has written acceptance tests. If a delivered milestone still fails them after two rounds of fixes, you get that milestone's fee back.
  1. /01

    Scope

    A call to agree the one function, the target FPGA and what done means.

  2. /02

    Quote

    A fixed price and a written scope, before any work starts.

  3. /03

    Build

    Design and verification against an independent reference model, with progress shared weekly.

  4. /04

    Hand over

    The design, the tests, the implementation results and a report in plain language.

We implement the design for your target FPGA and test it on your board with you.

Who owns the finished design is written into the agreement before we start.

Sensing chips for infrastructure

Detection chips for water, sanitation and electricity, designed from the physics of how each system fails. Raven-01, for sanitation, is our first. We are looking for pilot sites.

See Raven-01

Research

Published, physics based analysis of the semiconductor industry and of the problems our chips are built to solve. Each paper says what kind of evidence it rests on.

Read our research

What to send us

  • What is failing, or what you need the chip or FPGA to do.
  • Where it runs: the environment, the power available and any space limits.
  • Any timing you are working to.

A short email is enough to start. Talk to an engineer.

Have a problem a chip should solve?

Tell us what is failing and where. An engineer will reply within two working days.

Talk to an engineerRead our research

Opens an email to hello@napletech.online.